1. Field of the Invention
The present invention relates to a semiconductor storage device having fuse blocks each including a plurality of fuse pieces that are cuttable (disconnectable) for selection of alternative memory cells in place of defective memory cells.
2. Description of the Related Art
A semiconductor storage device is known that is provided with fuse blocks for selecting alternative memory cells in place of defective memory cells. For example, such device is disclosed in Japanese Patent No. 3099802. This patent was published on Oct. 29, 1999 in Japan with the publication (Kokai) number 11-297955.
FIG. 1 of the accompanying drawings depicts a conventional semiconductor storage device 1 having a plurality of fuse blocks. This device 1 is similar to the semiconductor storage device of Japanese Patent No. 3099802 in terms of fuse blocks. A gate array 10 is disposed between a memory cell array 5 and a memory cell array 6. A logic circuit 21 and fuse blocks 31 and 32 are arranged in line between the gate array 10 and the right memory cell array 5. Another logic circuit 22 and fuse blocks 33 and 34 are arranged in line between the gate array 10 and the left memory cell array 6. It should be noted that a plurality of fuse blocks (not depicted) are also provided next to the fuse blocks 32 and 34 in an actual arrangement. Each memory cell array 5, 6 has a plurality of memory cells.
Each of the fuse blocks 31 to 34 for example includes a plurality of fuse pieces (not depicted) for storing defective memory addresses of defective memory cells (not depicted) in the memory cell arrays 5 and 6. The blocks can store defective memory addresses corresponding to the defective memory cells based on the cutting mode that are obtained by selectively cutting the fuse pieces with laser beam irradiations.
Each of the logic circuits 21 and 22 is for example a circuit that, when a defective memory address set by each of the fuse blocks 31 to 34 matches a memory address indicated by an external memory access signal, selects one backup memory cell (not shown) corresponding to the defective memory address.
Between the gate array 10 and the logic circuit 21 and fuse blocks 31, 32 and between the gate array 10 and the logic circuit 22 and fuse blocks 33, 34 are arranged dedicated power-supply wires for the gate array 10, i.e., power-supply wires 41 and 42 for VSS supply and power-supply wires 51 and 52 for VDD supply. On top of the logic circuits 21 and 22 and the fuse blocks 31 to 34 are arranged dedicated power-supply wires for the logic circuits and the fuse blocks, i.e., power-supply wires 43 and 44 for VSS supply and power-supply wires 53 and 54 for VDD supply.
Supply wires 60-1 to 60-n (n is an integer greater than or equal to 2) are arranged to supply VSS potentials to transistors (not shown) in the gate array 10, and supply wires 65-1 to 65-n are arranged to supply VDD potentials to the transistors in the gate array 10. One end of each of the supply wires 60-1 to 60-n is connected to the power-supply wire 41, and the other end thereof is connected to the power-supply wire 42. One end of each of the supply wires 65-1 to 65-n is connected to the power-supply wire 51, and the other end thereof is connected to the power-supply wire 52.